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THX a lot for your detailed answer dchisholm!!! Look at the data and see how fast the samples rise to the final value. I think you should be more concerned about the other more prominant delays like the ADC conversion and acquisition, time taken to perform calculations on the data or to display it The on-chip filtering combined with a high oversampling ratio ratio reduces the external antialias requirements.

I’m surprised by your statement: User Control Panel Log out. So I can catch both of the bytes high and low in a time of approx ns: So I need only x2 Bytes to read in, but this has to pass very quick. Guest Super Member Total Posts: For your 16 MHz clock, this calculates to almost 34 uSec!! I am not certain that timing diagram Figure 7b is correct for your application. I can’t take a 16 bit latch to buffer the values, cause my design is already produced In that case – and assuming you can solve the synchronization problem between DRDY and the ‘ instruction cycle – there are just enough instruction cycles to work.


St Louis Mo Status: I see there is an expert on the other line I can’t be sure to catch the impuls cause it’s only during for ns. Hi burnmeister Without personally knowing your ADC chip, my guess is that the output is held in tri-state until either or both of the RD and CS lines are pulled low.

BSS (Siemens) – Sipmos Small-signal Transistor (n Channel Enhancement Mode), N-Channel

I hope the circuit will run next monday. The analog rise time of whatever limits the input bandwidth. In this case, you have bzs125 Gixy Super Member Total Posts: It would be very glad, if anyone can help me to understand the following timing diagramm. If this is true, it is datasheett unusable in your application.

If I understand the question from “burnmeister” correctly, it can be re-stated as: From the “General Description” section of the Data Sheet, “The analog input is continuously sampledeliminating the need for an external sample-and-hold. Thanks for the answers till now anyway!! Debug breakpoints automatically disabled 16F88 cannot set darasheet oscillator frequency beyond Data is avaliable during the low period of DRDY e.

It should take only a few seconds to tell if the 33uSec rise time is correct or not. Perhaps the third set of comments will only triple the confusion – I hope it doesn’t cause the confusion to be cubed! The AD is sampling continuously.

Trigger the microcontroller program off the square wave edge: Forums Posts Latest Posts. Or perhaps a combination of Figure 7b and Figure 7a. This is clearly unusable. Using a bit latch would only add to your delay. Why does my PIC32 run slower than expected? It will remain valid for nearly nSec, as mentioned above. It was invented, as the Data Sheet says, to put us grey-haired analog filter designers out of work.

  IEC 61960 1 PDF

There is not enough time to read the 16bit like this: I think you have beat us.

Datasheet «BSS 125»

You should talk with an Analog Devices Application Engineer who is familiar with this part and get an official explanation of this spec. I’m using this 1. If you have same good ideas, please go on Writing an email to an analog devices engineer is also a good idea i will do next week! Remember that if you use Pic16F7x families.

You already listed the fastest way to read two ports: Then i can monitor the ad-results in a fast way and make some experiments like you said! From “Circuit Description” in the Data Sheet: There must be a conversion time too or am I wrong?

I think all 3 of us are confused by the same question but from different viewpoints. According to the Data Sheet Section It might be time to do an experiment in your development lab. You may xatasheet the first value, but that’s OK sbs125 you’re looking for the impulse response over several dozen readings.

Increase the clock speed of the PIC This architecture of oversample-then-decimate-in-the-data-domain seems to be fairly common.